1. Field of Invention
The present invention relates to a fuse in a semiconductor device and to a fabricating method thereof, which provides a fuse that is easily melted and cut off by a low current.
2. Discussion of Related Art
FIG. 1A to FIG. 1G show cross-sectional views of fabricating a fuse in a semiconductor device, according to a related art.
Referring to FIG. 1A, integrated circuit portions 10 are formed on a semiconductor substrate 11. A MOS transistor 12 including a source and a drain region 14 and 15, which are surrounded by a LOCOS oxide layer 19, is formed in the substrate. By a conventional method, a planarized oxide layer 20 is formed on the LOCOS oxide layer 19 and transistor 12. The semiconductor substrate may be one of doped silicon, undoped silicon, or other semiconductor substances. Referring to FIG. 1B, a TiW layer 22, about 500 xc3x85 thick, is deposited on the oxide layer 20. An Al alloy layer 23, 2000 to 3000 xc3x85 thick, is deposited on the TiW layer 22. A TiW fuse is generated from the TiW layer 22, which will be explained in the following description. Referring to FIG. 1C, the Al alloy layer 23 is coated with a photoresist layer 25. Contact windows 26 are formed by photolithography. Referring to FIG. 1D, holes 26 are formed by removing the Al alloy layer 23, TiW layer 22 and oxide layer 20.
Referring to FIG. 1E, after the photoresist layer 25 has been removed, the holes 26 are filled up with TiW and CVD tungsten, forming contact posts 28 on the source and drain regions 14 and 15. Tungsten for the contact posts 28 uses the Al alloy layer 28 as an etch stop layer and is planarized by REB(resistive etch back), or the like.
Referring to FIG. 1F, a subsidiary Al alloy layer 30 is deposited. The subsidiary Al alloy layer 30 is coated with a photoresist layer 31. Then, leads are formed by etching the Al alloy layers 30 and 23 by lithography.
Referring to FIG. 1G, after the photoresist layer 31 has been removed, another photoresist layer 33 is formed on the above structure and patterned by lithography. The TiW layer for a fuse material is etched using the Al alloy layer as a mask, leaving a fuse part 34 between contact elements working as an electrical access.
Unfortunately, in the related art, the applied current or voltage necessary to activate the fuse is relatively high, since the bottom of the fuse pattern is planarized. Therefore, the fusing function fails to work well, due to the uniform thickness of the fuse material. Further, various fuse materials cause malfunction in the fusing function.
Accordingly, the present invention is directed to a fuse and a fabricating method thereof that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
The object of the present invention is to provide a fuse and a fabricating method thereof which provides a fuse easy to manufacture and which functions in a superior way.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention includes the steps of forming a device-isolating layer surrounding an active area on a semiconductor substrate of a first conductive type, forming a MOS transistor having a source and a drain of a second conductive type in the active area, forming a groove on the device-isolating layer to a predetermined depth, forming an insulating interlayer on the substrate including the groove wherein the insulating interlayer replicates a pattern of the groove, depositing a barrier metal for a fuse on the insulating interlayer including the replicated groove by sputtering, depositing Al on the barrier metal, forming a wire consisting of the Al and barrier metal by patterning the Al and barrier metal, and forming a fuse layer consisting of the barrier metal by removing the Al of the wire corresponding to the groove.
In another aspect, the present invention includes a semiconductor substrate, an insulating layer on the semiconductor substrate wherein a groove is patterned to a predetermined depth in an upper surface of the insulating layer, a fuse layer at sidewalls and on a bottom of the groove, and a wire connected electrically to the fuse layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.